System Designer’s Guide to… System Analysis, Chapter 2


Extract: System Designer’s Guide to… System Analysis, Chapter 2

Chapter 2: Challenges in the design and development of electronic systems
The exponential growth of data center infrastructure for computer networking has introduced many challenges, ranging from small ecosystems to high performance computing issues. There are many constraints on building data centers and updating the equipment there. Planning is essential to manage the increase in capacity in the existing data center space. The increase in the density of the racks disrupts the existing electrical distribution infrastructure. When more devices are added to the existing space, the temperature rises and the need for precision containment and cooling solutions arises. In addition, the components must be able to withstand higher temperatures. Managing the load capacity / phase power and the weight of the equipment is another challenge. Additionally, racks also have energy efficiency issues, and the depth of the racks can cause incompatibility with newer designs. While there are other challenges in the hardware and software context, such as implementing advanced 7nm nodes and verifying complex domain-specific architectures, this section primarily focuses on aspects of system analysis. Data centers require compute intensive devices in a small footprint. With a decrease in the size of the transistor, an advanced node is created. The small form factor brings several gains like higher density and faster switching. However, at the same time, advanced nodes take the complexity of design and integration to a new level.

Decreasing the metal pitch results in coupling effects and signal integrity problems. The increase in wire and via resistance requires more advanced and variable wire sizing and unraveling techniques to compensate. Server signals, chip complexity and cost, power management and electromigration, achievement of performance goals, lithography limitations, complexity and variability of processes in extraction, synchronization, integrity analysis Signal strength and modeling, package complexity, shorter time to market, and project management (engineers / project cost) are some of the critical challenges in advanced node chip design.

The advanced node creates chip layout design problems due to an irregular layout that causes routing congestion. In addition, the wide buses used for in-chip block communication increase congestion. In manufacturing, advanced nodes face lithography, process, and packaging issues. And due to the use of high-K metal grids (HKMG) and silicon-on-insulator (SoI) technology, foundry rules present relatively new complications. The use of stress and strain engineering causes varying electrical effects which depend on the characteristics of the layout. Rule-based metallic infill does not take into account multi-layered effects and therefore may lead to varying results. Dual-pattern technology has its ecosystem of problems. In addition, due to the increased complexity of lithography, conventional model-based optical proximity correction (OPC) and resolution enhancement (RET) techniques are not sufficient to provide the required silicon pattern fidelity. . Packaging issues can include thermal and stress issues due to die disaggregation, 3D stacking (3D-IC), and TSVs. The challenges of interdependence are not easy to manage. The electrical properties of a chip vary depending on the lithography, and the details of the process and packaging vary depending on the layout of the chip. From ground planning to approval, tools must interact to make countless adjustments and tradeoffs.

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